DRAMs use one or more arrays of memory cells arranged in rows and columns. Each of the rows of memory cells is activated by a corresponding row line, which is selected from a row address. A pair of complementary digit lines are provided for each column of the array, and a sense amplifier coupled to the digit lines for each column is enabled responsive to a respective column address. The sense amplifier senses a small voltage differential between the digit lines and amplifies such voltage differential. In a “folded digit line” memory architecture, the complementary digit lines extend through the same array. In the typical folded digit line architecture, the memory cells in the odd rows are coupled to one of the digit lines in each column, and the memory cells in the even rows are coupled to the other of the digit lines in each column. However, other connection arrangements are also possible. In a folded digit line architecture, a sense amplifier senses a voltage differential between a high voltage level coupled to a digit line by a memory cell in an one row and a low voltage level coupled to a complementary digit line by a memory cell in a different row as either a logic “1” or a logic “0”.
Both digit lines of each column are typically precharged to one-half the supply voltage VCC, a voltage known as “DVC2,” prior to being coupled to a memory cell. Coupling the memory cell to the digit line causes the voltage on the digit line to increase slightly above DVC2 or decreased slightly below DVC2. The sense amplifier compares this altered voltage to the voltage DVC2 on the complementary digit line and then drives the digit line coupled to the memory cell to the fill high or low logic level, thereby restoring the voltage on the memory cell to the voltage corresponding to the logic level stored in the memory cell. The logic level stored in the memory cell can then be read by determining the differential voltage between the digit lines.
As is well-known in the art. DRAM memory cells must be periodically refreshed to avoid a loss of data The memory cells in a row can be refreshed by simply coupling the memory cells in the row to one of the digit lines after enabling the sense amplifiers. The sense amplifiers then restore the voltage level on the memory cell capacitor to a voltage level corresponding to the stored data bit. The permissible time between refreshes without losing data depends upon a variety of factors, including the rate at which charge is dissipated in memory cell capacitors. When a memory cell capacitor is excessively discharged from a high logic level, generally equal to the supply voltage, VCC, or excessively charged from a low logic level, generally ground, its logic level of can no longer be accurately read.
One problem with conventional DRAMs results from individual memory cells becoming defective such as, for example, as a result of a shorted memory cell capacitor. A memory access to a defective memory cell must be redirected to a different memory cell so that data will be accurately read from a DRAM. Redundant rows and columns of memory cells are typically provided for this purpose. However, a substantial amount of an additional circuitry must be provided to redirected memory accesses to redundant memory cells.
One approach to solving this defective memory cell problems is disclosed in U.S. Pat. No. 6,044,029, which is incorporated herein by reference. As described therein, memory cells are effectively “repaired” by writing data bits to and reading data bits from a column of memory cells by coupling two memory cells in respective rows to the same digit line or different digit lines for that column. Thus, for example, the memory cell in an even row is coupled to a digit line and the memory cell in an odd row is coupled to the complimentary digit line. If one of the memory cells is defective, the charge from the non-defective memory cell can change the voltage on the digit line to be detected by the sense amplifier. Although using two memory cells to store in each bit of data provides the advantage discussed above, it has the disadvantage of reducing the capacity of a memory array by 50 percent.
Another disadvantage of operating in a half density mode as described in U.S. Pat. No. 6,044,029 stems from the difficulty of interfacing the DRAM to computer circuitry when the DRAM is operating in the half density mode. A conventional dual mode, half density/full density 128 MB synchronous DRAM (“SDRAM”) is organized into 4 banks each having 4096 rows and 1024 columns. When this conventional 128 MB SDRAM is operating in the half density mode, it is organized into 4 banks each having 4096 rows and only 512 columns. Thus, when operating in the full density mode, there will be 12 bits of row address RA0-RA11 and 10 bits of column address CA0-CA9. When operating in the half density mode, there will still be 12 bits of row address RA0-RA11 but only 9 bits of column address CA0-CA8. However, the SDRAM described in U.S. Pat. No. 6,044,029 operates in the half density mode in a manner that is different from the operation of conventional dual mode SDRAMs. The SDRAM described in U.S. Pat. No. 6,044,029 has the same addressing configuration as the conventional SDRAM when operating in the full density mode, i.e., 12 bits of row address RA0-RA11 and 10 bits of column address CA0-CA9. However, when operating in the half density mode, the SDRAM described in U.S. Pat. No. 6,044,029 has the same number of column address bits, i.e., 10 column address bits CA0-CA9, but half as many row address bits, i.e., 11 row address bits RA0-RA10, since 2 rows of memory cells are used to store each row of data. As a result, systems designed to operate with conventional SDRAMs operating in a half density mode provide RA0-RA11 row address bits and CA0-CA8 column address bits rather than the RA0-RA10 row address bits and the CA0-CA9 column address bits required by SDRAMs of the type described in U.S. Pat. No. 6,044,029. For this reason, it can be difficult to interface SDRAMs of the type described in U.S. Pat. No. 6,044,029 to systems that have been designed for conventional dual mode SDRAMs.
There is therefore a need for solutions to the above-described problems with and limitations of DRAM's of the type described in U.S. Pat. No. 6,044,029, thus improving the usefulness of such DRAM's.